Author: Tushar Krishna, Georgia Institute of Technology
Hyoukjun Kwon, Georgia Institute of Technology
Angshuman Parashar, NVIDIA
Michael Pellauer, NVIDIA
Ananda Samajdar, Georgia Institute of Technology
Keywords: artificial intelligence (AI), deep learning, deep neural networks (DNN), convolutional neural networks (CNN), general matrix multiplication (GEMM), hardware/software co-design, deep neural network scheduling (DNN scheduling), deep neural network mapping (DNN mapping), dataflow, data orchestration, spatial accelerators, architecture, hardware
Abstract: This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore’s Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.